Tailoring IGZO-TFT architecture for capacitorless DRAM, demonstrating > 10³s retention, >10¹¹ cycles endurance and L_g scalability down to 14nm

Abstract

We demonstrate a fully 300-mm BEOL-compatible IGZO-based capacitorless DRAM cell with >10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> s retention and >10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> endurance lifetime. We reveal the impact of the IGZO-TFT architecture on the memory performance of 2TOC structures, and we select a gate-last integration scheme with buried oxygen tunnel and self-aligned contacts. With this architecture, we demonstrate >100s retention time down to scaled <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{L}_{\mathrm{g}}\approx 14$</tex> nm. We prove that by decreasing the gate dielectric thickness the retention time can be significantly improved, while the IGZO thickness scaling enables to skip the defect passivation anneal. We also demonstrate the functionality of 2TOC cells with conformal IGZO deposition, paving the way for full BEOL 3D DRAM integration.