K. Henson

High performance 14nm SOI FinFET CMOS technology with 0.0174µm<sup>2</sup> embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 128 citations

High-Performance High-¿/Metal Gates for 45nm CMOS and Beyond with Gate-First Processing

M. Chudzik, B. Doris, R. Mo et al. · 2007 · 75 citations

Engineering, Vlsi Design, Gate-first Processing +16

Limitations of shift-and-ratio based L/sub eff/ extraction techniques for MOS transistors with halo or pocket implants

H. van Meer, K. Henson, Junyi Lyu et al. · IEEE Electron Device Letters · 2000 · 47 citations

Device Modeling, Electrical Engineering, Engineering +12

A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS

Richard Lindsay, B. J. Pawlak, J. A. Kittl et al. · MRS Proceedings · 2003 · 42 citations

Electrical Engineering, Physical Design (Electronics), Engineering +8

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper

B. Greene, Qingqing Liang, K. Amarnath et al. · Symposium on VLSI Technology · 2006 · 40 citations

Engineering, Vlsi Design, Nm Ground Rules +16