H. van Meer

Influence of device engineering on the analog and RF performances of SOI MOSFETs

Valeriya Kilchytska, Amaury Nève, Laurent Vancaillie et al. · IEEE Transactions on Electron Devices · 2003 · 227 citations

Engineering, Analog Design, Rf Performances +17

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

P. Agnello, T. Ivers, C. Warm et al. · 2006 · 115 citations

Engineering, Vlsi Design, Enhanced Strain +21

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta et al. · 2005 · 65 citations

Electrical Engineering, Engineering, Vlsi Design +15

Limitations of shift-and-ratio based L/sub eff/ extraction techniques for MOS transistors with halo or pocket implants

H. van Meer, K. Henson, Junyi Lyu et al. · IEEE Electron Device Letters · 2000 · 47 citations

Device Modeling, Electrical Engineering, Engineering +12

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper

B. Greene, Qingqing Liang, K. Amarnath et al. · Symposium on VLSI Technology · 2006 · 40 citations

Engineering, Vlsi Design, Nm Ground Rules +16