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High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper
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2006
Year
EngineeringVlsi DesignNm Ground RulesHigh Performance 32NmIntegrated CircuitsSilicon On InsulatorInterconnect (Integrated Circuits)Semiconductor DeviceSoi CmosElectrical EngineeringComputer EngineeringSemiconductor Device FabricationMicroelectronicsUltra Low-kLow-power ElectronicsVlsi ArchitectureApplied PhysicsNm Immersion LithographyDual Stress Liner
This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 µm2. V min operation down to 0.6 V in a 16Mb SRAM array test vehicle has been demonstrated. Aggressive ground rules are achieved with 193 nm immersion lithography. High performance is enabled by hig-hk/metal gate plus innovation on strained silicon elements including embedded SiGe and dual stress liner (DSL). Gate lengths down to 25 nm have been demonstrated enabling performance without the power penalty from gate capacitance. AC drive currents of 1.55 mA/um and 1.22 mA/um have been achieved at an off-state of 100 nA/µm and V DD of 1 V for NFET and PFET, respectively. For the first time, we have also demonstrated that SOI maintains performance benefit over bulk silicon in high-k/metal gate and 32 nm ground rules.