Nandar Su

Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects

Srinivasa Rao Vempati, Nandar Su, Chee Houe Khong et al. · 2009 · 42 citations

3-D Silicon Die, Flip Chip Technology, Engineering +17

Embedded wafer level packages with laterally placed and vertically stacked thin dies

Gaurav Sharma, Vempati Srinivas Rao, Aditya Kumar et al. · 2009 · 34 citations

Engineering, Mechanical Engineering, Interconnect (Integrated Circuits) +18

High Quality and Low Loss Millimeter Wave Passives Demonstrated to 77-GHz for SiP Technologies Using Embedded Wafer-Level Packaging Platform (EMWLP)

Ying Ying Lim, Xianghua Xiao, Srinivasa Rao Vempati et al. · IEEE Transactions on Advanced Packaging · 2010 · 33 citations

Electrical Engineering, Millimeter Wave Technology, Engineering +15

Development of Fine Pitch Solder Microbumps for 3D Chip Stacking

Aibin Yu, Aditya Kumar, Soon Wee Ho et al. · 2008 · 28 citations

Engineering, Mechanical Engineering, Ultra Fine Pitch +20

3D packaging with through ilicon via (TSV) for electrical and fluidic interconnections

Navas Khan, H.Y. Yu, Tan Siow Pin et al. · 2009 · 23 citations

Engineering, Chip Carrier, Liquid Metal Cooling +19