Development of Fine Pitch Solder Microbumps for 3D Chip Stacking

Abstract

Developments of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies are discussed in this paper. CuSn solder microbumps with 25 ¿m in pitch are fabricated at wafer level by electroplating method and the total thicknesses of the platted Cu and Sn are 10 ¿m. After plating, the micro bumps on the Si chip are reflowed at 265°C and the variation of bump height measured within a die is less than 5%. The under bump metallurgy (UBM) layer on the Si carrier used is electroless plated nickel and immersion gold (ENIG) with total thickness less than 5 ¿m. Assembly of the Si chip and the Si carrier is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained. After assembly, underfill process is carried out to fill the gap and a void free underfilling is achieved using an underfill material with fine filler size.