H. Rathore

Full copper wiring in a sub-0.25 μm CMOS ULSI technology

D. Edelstein, J. Heidenreich, R. Goldblatt et al. · 2002 · 350 citations

3D Ic Architecture, Electrical Engineering, Cu Wiring +8

A high performance liner for copper damascene interconnects

D. Edelstein, Cyprian Uzoh, C. Cabral et al. · 2001 · 90 citations

Materials Science, 3D Ic Architecture, Electrical Engineering +13

Scaling effect on electromigration in on-chip Cu wiring

C.‐K. Hu, R. Rosenberg, H. Rathore et al. · 2003 · 66 citations

Engineering, On-chip Cu Wiring, Void Growth +16

Electromigration improvements with titanium underlay and overlay in Al(Cu) metallurgy

J.J. Estabil, H. Rathore, E. Levine · 2002 · 23 citations

Engineering, Interconnect (Integrated Circuits), Anodizing +16

Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL

D. Edelstein, H. Rathore, C. Davis et al. · 2004 · 23 citations

Engineering, Chip-package Reliability Stress, Interconnect (Integrated Circuits) +20