A high performance liner for copper damascene interconnects

Abstract

We describe a liner for Cu-Damascene multilevel ULSI interconnects, which satisfies all the important requirements for a high performance and reliable Cu interconnect technology. This liner is implemented in the first manufacturing process to produce and ship CMOS chips with Cu interconnects. The liner is a bilayer from a family of hcp/bcc-TaN followed by bcc-Ta (/spl alpha/-Ta), deposited sequentially in a single PVD chamber from a pure Ta target, using Ar and N/sub 2/ sputtering gases. This bilayer simultaneously maximizes adhesion to the interlevel dielectric and the Cu fill, and has very low in-plane resistivity (/spl sim/30-60 /spl mu//spl Omega/-cm, depending on TaN/Ta thicknesses). These qualities produce high-yield, highly reliable, and electromigration-redundant Cu interconnects.