Journal of Microelectronics and Electronic Packaging · 2012 · 19 citations · 0 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsSemiconductor DevicesVlsi DesignChip PackagingCmos Circuit DesignIntegrated Circuit DesignIntegrated Circuit FabricationSemiconductor Device MaterialsVery-large-scale Integration Layout3D Integrated CircuitsAdvanced PackagingCmos Fabrication ProcessesPlatingSeed LayersThree-dimensional Integrated Circuit LayoutThree-dimensional IntegrationThrough-silicon Vias
In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu plating of blind TSVs on 300 mm wafers for 3D integration are investigated. Emphasis is placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, the leakage current of the fabricated Cu-filled TSVs is measured. Furthermore, cross sections and SEM of the fabricated TSVs are examined.