Cha-Hsin Lin

Charge-Trapping-Type Flash Memory Device With Stacked High-$k$ Charge-Trapping Layer

Ping-Hung Tsai, Kuei‐Shu Chang‐Liao, Te-Chiang Liu et al. · IEEE Electron Device Letters · 2009 · 41 citations

Semiconductors, Electrical Engineering, Electronic Devices +15

Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration

Chien-Ying Wu, Shang-Chun Chen, Pei-Jer Tzeng et al. · Journal of Microelectronics and Electronic Packaging · 2012 · 17 citations · Full text

Engineering, Blind Tsvs, Wafer Scale Processing +17

Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions

Erh-Hao Chen, Tzu‐Chien Hsu, Cha-Hsin Lin et al. · 2013 · 16 citations

Engineering, Mechanical Engineering, Via-last Tsv Process +17

HfO₂/HfAlO/HfO₂ Nanolaminate Charge Trapping Layers for High-Performance Nonvolatile Memory Device Applications

S. Maikap, Pei-Jer Tzeng, Ting‐Yu Wang et al. · Japanese Journal of Applied Physics · 2007 · 11 citations

Non-volatile Memory, Electrical Engineering, Chemical Engineering +14

Low Voltage Operation of High-κ HfO₂/TiO₂/Al₂O₃ Single Quantum Well for Nanoscale Flash Memory Device Applications

S. Maikap, Ting‐Yu Wang, Pei-Jer Tzeng et al. · Japanese Journal of Applied Physics · 2008 · 10 citations

Engineering, Memory Characteristics, Low Voltage Operation +19