Concepedia

Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions

Erh-Hao Chen, Tzu‐Chien Hsu, Cha-Hsin Lin, Pei-Jer Tzeng, Chung-Chih Wang, Shang-Chun Chen, Jui‐Chin Chen, Chien‐Chou Chen, Yu-Chen Hsin, Po-Chih Chang,

2013 · 16 citations · 4 references

DOI

Concepts

Abstract

Fine-pitch backside via last through silicon via (TSV) process flow is demonstrated as a qualified candidate to be used in the construction of 3D-IC structure. Glue and its bonding conditions are critical to the final yield of the process. Different glues and temporary bonding conditions are investigated to find out the optimized stable process flow. Different daisy chain lengths are used to evaluate the maturity of the backside via last TSV process.

References

4

Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers

Yu-Chen Hsin, Chien‐Chou Chen, John H. Lau et al. · 2011 · 39 citations

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Effects of Slurry in Cu Chemical Mechanical Polishing (CMP) of TSVs for 3-D IC Integration

Jui‐Chin Chen, John H. Lau, Pei-Jer Tzeng et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2012 · 24 citations

, , +14

Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration

Chien-Ying Wu, Shang-Chun Chen, Pei-Jer Tzeng et al. · Journal of Microelectronics and Electronic Packaging · 2012 · 19 citations · Full text

, , +17

Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration

Chien-Ying Wu, Shang-Chun Chen, Pei-Jer Tzeng et al. · IMAPSource Proceedings · 2011 · 12 citations

, , +17