Yu-Chen Hsin - Concepedia

Author

Yu-Chen Hsin

Industrial Technology Research Institute

Also Known As

Shih, Cheng-Yi, Y. -C. Hsin, Y. C. Hsin, Y.-C. Hsin, Yu-Chen Hsin

Publications

389

Citations

H-Index

Concepts

All Affiliations

Industrial Technology Research Institute ITRI International National Taiwan University Taiwan Semiconductor Manufacturing Company (United States)

About

Yu-Chen Hsin is an author at Industrial Technology Research Institute specializing in engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	10	11	230
2	Electrical Engineering	10	10	214
3	Applied Physics	9	9	186
4	Computer Engineering	5	5	108
5	Natural Sciences	3	3	74

Yu-Chen Hsin

Publications

330

Citations

H-Index

Page 1

	Year	Citations
High speed (1ns) and low voltage (1.5V) demonstration of 8Kb SOT-MRAM array M. Y. Song, C. M. Lee, Shao‐Yu Yang, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Non-volatile MemoryEngineeringSpintronic MaterialLow ResistivitySpin Dynamic	2022	43
Pulse-Width and Temperature Effect on the Switching Behavior of an Etch-Stop-on-MgO-Barrier Spin-Orbit Torque MRAM Cell S. Z. Rahaman, I‐Jung Wang, Tian-Yue Chen, IEEE Electron Device Letters Non-volatile MemoryEngineeringMagnetic ResonanceSwitching BehaviorSpintronic Material	2018	39
Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers Yu-Chen Hsin, Chien‐Chou Chen, John H. Lau,	2011	38
Process integration of 3D Si interposer with double-sided active chip attachments Pei-Jer Tzeng, John H. Lau, Chau‐Jie Zhan, Process IntegrationEngineeringDevice IntegrationPassive InterposerWafer Scale Processing	2013	24
Size-Dependent Switching Properties of Spin-Orbit Torque MRAM With Manufacturing-Friendly 8-Inch Wafer-Level Uniformity S. Z. Rahaman, I‐Jung Wang, Ding-Yeong Wang, IEEE Journal of the Electron Devices Society Non-volatile MemoryEngineeringEmerging Memory TechnologySize-dependent Switching PropertiesThermal Stability Criteria	2020	20
Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW) John H. Lau, Cheng Zhan, P. J. Tzeng, Journal of Microelectronics and Electronic Packaging Mm Multi-project WaferEngineeringDevice IntegrationIc Integration SipFeasibility Study	2011	20
Impact of slurry in Cu CMP (chemical mechanical polishing) on Cu topography of Through Silicon Vias (TSVs), re-distribution layers, and Cu exposure J. C. Chen, P. J. Tzeng, Sheng‐Chih Chen, EngineeringCu CmpMechanical EngineeringCu ExposureBackside Isolation	2011	18
Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration Chien-Ying Wu, Shang-Chun Chen, Pei-Jer Tzeng, Journal of Microelectronics and Electronic Packaging EngineeringBlind TsvsWafer Scale ProcessingAdvanced Packaging (Semiconductors)Nanoelectronics	2012	17
Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions Erh-Hao Chen, Tzu‐Chien Hsu, Cha-Hsin Lin, EngineeringMechanical EngineeringVia-last Tsv ProcessInterconnect (Integrated Circuits)Fine-pitch Backside	2013	16
High RA Dual-MTJ SOT-MRAM devices for High Speed (10ns) Compute-in-Memory Applications M. Y. Song, Kuo-Lung Chen, K. M. Chen,	2023	15

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