Chau‐Jie Zhan - Concepedia

Author

Chau‐Jie Zhan

Industrial Technology Research Institute

Also Known As

Chau-Jie Zhan, Chau‐Jie Zhan

Publications

630

Citations

H-Index

Concepts

All Affiliations

Industrial Technology Research Institute ITRI International Corning (United States)National Taiwan University Chung Yuan Christian University

About

Chau‐Jie Zhan is an author at Industrial Technology Research Institute specializing in microelectronics, electronic packaging, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	15	19	464
2	Electrical Engineering	13	16	407
3	Computer Engineering	9	9	241
4	Applied Physics	6	6	179
5	Materials Engineering	3	3	81

Chau‐Jie Zhan

Publications

484

Citations

H-Index

Page 1

	Year	Citations
Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking Yu-Min Lin, Chau‐Jie Zhan, Jing-Ye Juang, EngineeringInterconnect (Integrated Circuits)Wafer Scale ProcessingAdvanced Packaging (Semiconductors)Electromigration Test	2011	53
Assembly and reliability characterization of 3D chip stacking with 30&#x03BC;m pitch lead-free solder micro bump interconnection Chau‐Jie Zhan, Chun-Chih Chuang, Jing-Ye Juang, EngineeringFine PitchIntegrated CircuitsSolder BumpInterconnect (Integrated Circuits)	2010	50
Through-Silicon Hole Interposers for 3-D IC Integration John H. Lau, Ching-Kuan Lee, Chau‐Jie Zhan, IEEE Transactions on Components Packaging and Manufacturing Technology Top ChipThrough-silicon Hole InterposersElectrical EngineeringChip-scale PackageEngineering	2014	45
Performance and Process Comparison between Glass and Si Interposer for 3D-IC Integration Chun-Hsien Chien, Ching-Kuan Lee, Hsun Yu, IMAPSource Proceedings EngineeringDevice IntegrationProcess ComparisonWafer Scale ProcessingAdvanced Packaging (Semiconductors)	2013	42
Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30&#x03BC;m pitch lead-free solder micro bumps and reliability characterization Chau‐Jie Zhan, Jing-Ye Juang, Yu-Min Lin, Materials Science3D Ic ArchitectureElectrical EngineeringWafer Scale ProcessingEngineering	2011	36
Process integration of 3D Si interposer with double-sided active chip attachments Pei-Jer Tzeng, John H. Lau, Chau‐Jie Zhan, Process IntegrationEngineeringDevice IntegrationPassive InterposerWafer Scale Processing	2013	24
Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design Yu-Jen Chang, Hao-Hsiang Chuang, Yi-Chang Lu, 3-D IcNovel CrosstalkEngineeringPower ElectronicsInterconnect (Integrated Circuits)	2012	23
Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP Chau‐Jie Zhan, Pei-Jer Tzeng, John H. Lau, 3D Ic ArchitectureCu RevealingEngineeringIc Integration System-in-packageChip-scale Package	2012	21
Performance and process characteristic of glass interposer with through-glass-via(TGV) Chun-Hsien Chien, Hsun Yu, Ching-Kuan Lee, EngineeringPrimary ApproachOrganic SubstratesInterconnect (Integrated Circuits)Glass-ceramic	2013	20
Effect of metal finishing fabricated by electro and Electroless plating process on reliability performance of 30&#x03BC;m-pitch solder micro bump interconnection Jing-Ye Juang, Shin‐Yi Huang, Chau‐Jie Zhan, EngineeringMechanical EngineeringInterconnect (Integrated Circuits)Wafer Scale ProcessingAdvanced Packaging (Semiconductors)	2013	20

Page 1