Jing-Ye Juang - Concepedia

Author

Jing-Ye Juang

Industrial Technology Research Institute

Also Known As

Jing-Ye Juang

Publications

277

Citations

H-Index

Concepts

All Affiliations

Industrial Technology Research Institute National Tsing Hua University Feng Chia University

About

Jing-Ye Juang is an author at Industrial Technology Research Institute specializing in electrical engineering, microelectronics, and electronic packaging.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	6	6	220
2	Electrical Engineering	6	6	220
3	Materials Science	4	4	159
4	Applied Physics	2	2	83
5	Computer Engineering	2	2	81

Jing-Ye Juang

Publications

230

Citations

H-Index

Page 1

	Year	Citations
Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking Yu-Min Lin, Chau‐Jie Zhan, Jing-Ye Juang, EngineeringInterconnect (Integrated Circuits)Wafer Scale ProcessingAdvanced Packaging (Semiconductors)Electromigration Test	2011	53
Assembly and reliability characterization of 3D chip stacking with 30&#x03BC;m pitch lead-free solder micro bump interconnection Chau‐Jie Zhan, Chun-Chih Chuang, Jing-Ye Juang, EngineeringFine PitchIntegrated CircuitsSolder BumpInterconnect (Integrated Circuits)	2010	50
Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30&#x03BC;m pitch lead-free solder micro bumps and reliability characterization Chau‐Jie Zhan, Jing-Ye Juang, Yu-Min Lin, Materials Science3D Ic ArchitectureElectrical EngineeringWafer Scale ProcessingEngineering	2011	36
Drop Impact Reliability Analysis of 3-D Chip-on-Chip Packaging: Numerical Modeling and Experimental Validation Hsien‐Chie Cheng, Hsin-Kai Cheng, Su‐Tsai Lu, IEEE Transactions on Device and Materials Reliability EngineeringExperimental ValidationMechanical EngineeringReliability EngineeringAdvanced Packaging (Semiconductors)	2013	31
Effects of Bonding Parameters on the Reliability of Fine-Pitch Cu/Ni/SnAg Micro-Bump Chip-to-Chip Interconnection for Three-Dimensional Chip Stacking Su‐Tsai Lu, Jing-Ye Juang, Hsien‐Chie Cheng, IEEE Transactions on Device and Materials Reliability EngineeringThree-dimensional Chip StackingIntegrated CircuitsInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors)	2012	30
Effect of metal finishing fabricated by electro and Electroless plating process on reliability performance of 30&#x03BC;m-pitch solder micro bump interconnection Jing-Ye Juang, Shin‐Yi Huang, Chau‐Jie Zhan, EngineeringMechanical EngineeringInterconnect (Integrated Circuits)Wafer Scale ProcessingAdvanced Packaging (Semiconductors)	2013	20
Development of high throughput adhesive bonding scheme by wafer-level underfill for 3D die-to-interposer stacking with 30µm-pitch micro interconnections Yu‐Wei Huang, Chia-Wen Fan, Yu-Min Lin,	2015	10

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