Performance and Process Comparison between Glass and Si Interposer for 3D-IC Integration

Abstract

Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed, and has been compared in complete processes and electrical/thermal characteristics with silicon interposer. In order to simulate and measure the electrical/thermal performance, patterned interposer wafer with 30μm diameter and 100μm depth Cu-filled TSVs are designed and prepared in advance. Key technologies include via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass thinning and backside RDL formation were well developed and integrated to perform for comparison. 30μm via, 60μm pitch, RDL line/space 20μm/30um, 100μm thin wafer/glass and 15um micro-bumping been successfully integrated in the integration platform. The glass interposer was characterized and assessed to have excellent electrical performance and is potentially to be applied for 3D product applications.