Abnormal Two-Stage Degradation on P-Type Low-Temperature Polycrystalline-Silicon Thin-Film Transistor Under Hot Carrier Conditions

Abstract

In this study, an abnormal two-stage degradation of low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) on a polyimide flexible substrate after hot carrier stress was investigated. The degradation mechanism was divided into two stages. In the first stage, the increases in capacitance in the off region and transconductance are caused by impact ionization induced electron trapping into the gate insulator (GI) at the drain edge. Furthermore, the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula>) shift in the positive direction is caused by electrons flowing back to the source side and trapping into the buffer that induces source barrier lowing. The second stage of degradation, including a <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula> shift in the negative direction and a decrease in the transconductance is caused by Joule heating induced negative bias temperature instability (NBTI). Furthermore, NBTI hardly occurs behind the pinch off in the channel and fixed oxide charge does not compensate the trapped electron at drain side which is induced in the first stage.