A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node

Abstract

SRAM bitcell area reduction, lower SRAM parasitic resistance, and higher drive strength are necessary to continue with technology scaling. Nanosheet (NSH) technology improves SRAM cell write-ability by having 50 mV more write trip point (WTP) than FinFET (FF) SRAM due to reduced bit line (BL) resistance (due to wider metal CD) and more drive current strength (more than 15%) than FF for the same leakage. However, due to higher bitcell area (20% larger), BL, and word line (WL) parasitic capacitance than FF, NSH SRAM would not compete with FF SRAM in terms of the read delay (26% more delay) and energy at the 3-nm technology node. PFET to NFET (PN) spacing, composed of gate cut, gate extension, and Fin pitch in an SRAM bitcell, is critical for SRAM cell height because it can take ~46% of the 111 SRAM total cell height. The forksheet (FSH), achieving extremely scaled PN space in SRAM bitcell due to device structure with limited additional processing complexity, reduces the SRAM bitcell area. As a result, BL and WL parasitics reduce and improve the SRAM read delay and stability. FSH SRAM saves 6% area benefit and achieves 24% lesser read delay than FF high density (HD) SRAM.