2018 · 18 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice CharacterizationDevice ModelingDevice SimulationIntegrated Circuit DesignDamage Mechanism AnalysisGate Oxide DegradationMetal-oxide-semiconductor Field-effect Transistor Modeling
In this paper, a new mechanism of signal path charging damage is observed across a separated power domain interface from the non-DNW (Deep N-Well) to DNW region. This damage mechanism is unlike the damage outside DNW from the DNW to non-DNW region unveiled in our previous work. It is found that damage takes place inside the DNW and both NMOS and PMOS transistors are impacted instead of NMOS only. A model for the damage mechanism is proposed and verified comprehensively using test patterns in a 40nm logic process combined with SPICE simulations. Several protection schemes are proposed to avoid this new mechanism of charging damage.
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Shih‐Hung Chen, Ming-Dou Ker, Hsiang-Pin Hung · IEEE Transactions on Device and Materials Reliability · 2008 · 29 citations