Shih‐Hung Chen

A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

Shih‐Hung Chen, Hang-Ting Lue, Yen-Hao Shih et al. · 2012 · 39 citations

Engineering, Vlsi Design, Computer Architecture +16

Implementation of <i>Initial-On</i> ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology

Ming‐Dou Ker, Shih‐Hung Chen · IEEE Journal of Solid-State Circuits · 2007 · 30 citations

Low-power Electronics, Hardware Security, Electrical Engineering +12

Overview of 3D NAND Flash and progress of vertical gate (VG) architecture

Hang-Ting Lue, Shih‐Hung Chen, Yen-Hao Shih et al. · 2012 · 29 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +12

Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses

Shih‐Hung Chen, Ming-Dou Ker, Hsiang-Pin Hung · IEEE Transactions on Device and Materials Reliability · 2008 · 29 citations

Electrical Engineering, Engineering, Separated Power Domains +11

Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs

Shih‐Hung Chen, Ming-Dou Ker · IEEE Transactions on Circuits & Systems II Express Briefs · 2009 · 29 citations

Low-power Electronics, Electrical Engineering, Engineering +11