Yen-Hao Shih - Concepedia

Author

Yen-Hao Shih

Macronix International (Taiwan)

Also Known As

Y.C. Shih, Yen-Hao Shih, Yen-hao Shih

Publications

958

Citations

H-Index

Concepts

All Affiliations

Macronix International (Taiwan)National Tsing Hua University National Yang Ming Chiao Tung University Fu Jen Catholic University IBM Research - Almaden

About

Yen-Hao Shih is an author at Macronix International (Taiwan) specializing in engineering, microelectronics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	18	23	845
2	Applied Physics	15	16	682
3	Computer Engineering	14	16	429
4	Social Sciences	1	1	24
5	Computer Science	1	1	15

Yen-Hao Shih

Publications

890

Citations

H-Index

Page 1

	Year	Citations
Phase change materials and their application to random access memory technology Simone Raoux, R. M. Shelby, Jean Jordan‐Sweet, Microelectronic Engineering Materials ScienceMaterials EngineeringNon-volatile MemoryEngineeringPhase Change Materials	2008	152
BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability Hang-Ting Lue, Szu-Yu Wang, Erh-Kun Lai, SemiconductorsNon-volatile MemoryElectrical EngineeringElectronic DevicesEngineering	2006	134
Radically extending the cycling endurance of Flash memory (to &#x003E; 100M Cycles) by using built-in thermal annealing to self-heal the stress-induced damage Hang-Ting Lue, Pei-Ying Du, Chih‐Ping Chen, Non-volatile MemoryEngineeringTunnel OxideEmerging Memory TechnologyComputer Architecture	2012	59
Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D <sc>NAND</sc> Flash Memory Devices Yi‐Hsuan Hsiao, Hang-Ting Lue, Wei-Chen Chen, IEEE Transactions on Electron Devices Non-volatile MemoryEngineeringVlsi DesignEmerging Memory TechnologyElectrical Behavior	2014	44
A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts Shih‐Hung Chen, Hang-Ting Lue, Yen-Hao Shih, EngineeringVlsi DesignComputer ArchitectureStaircase ContactsPhysical Design (Electronics)	2012	39
Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations Chun-Hsiung Hung, Meng‐Fan Chang, Yih-Shan Yang, IEEE Journal of Solid-State Circuits Non-volatile MemoryElectrical EngineeringEngineeringNanoelectronicsBitline Capacitance	2015	37
An on-chip temperature sensor by utilizing a MOS tunneling diode Yen-Hao Shih, Jenn‐Gwo Hwu IEEE Electron Device Letters Simple Metal-oxide-semiconductorMos DiodeElectrical EngineeringEngineeringTunneling Microscopy	2001	35
Distribution of nanoscale nuclei in the amorphous dome of a phase change random access memory Bong-Sub Lee, Kristof Darmawikarta, Simone Raoux, Applied Physics Letters EngineeringNucleation TheoryEmerging Memory TechnologyAmorphous DomePhase Change Memory	2014	32
Overview of 3D NAND Flash and progress of vertical gate (VG) architecture Hang-Ting Lue, Shih‐Hung Chen, Yen-Hao Shih, Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringVlsi Design	2012	29
Modeling the variability caused by random grain boundary and trap-location induced asymmetrical read behavior for a tight-pitch vertical gate 3D NAND Flash memory using double-gate thin-film transistor (TFT) device Yi‐Hsuan Hsiao, Hang-Ting Lue, Wei-Chen Chen, Device ModelingGrain Boundary CreatesElectrical EngineeringNon-volatile MemoryEngineering	2012	28

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