Optimal Design Methods to Transform 3D NAND Flash into a High-Density, High-Bandwidth and Low-Power Nonvolatile Computing in Memory (nvCIM) Accelerator for Deep-Learning Neural Networks (DNN)

Hang-Ting Lue, Po-Kai Hsu, Ming‐Liang Wei, +5

Non-volatile MemoryElectrical EngineeringOptimal Design MethodsEngineeringHardware Acceleration +12

A high performance phase change memory with fast switching speed and high temperature retention by engineering the Ge<inf>x</inf>Sb<inf>y</inf>Te<inf>z</inf> phase change material

Huai‐Yu Cheng, T. H. Hsu, Simone Raoux, +12

EngineeringComputer ArchitecturePhase Change MemoryNew MaterialMemory Devices +15

Radically extending the cycling endurance of Flash memory (to > 100M Cycles) by using built-in thermal annealing to self-heal the stress-induced damage

Hang-Ting Lue, Pei-Ying Du, Chih‐Ping Chen, +5

Non-volatile MemoryEngineeringTunnel OxideEmerging Memory TechnologyComputer Architecture +14

A low power phase change memory using thermally confined TaN/TiN bottom electrode

J.Y. Wu, M. Breitwisch, Sang‐Bum Kim, +15

Non-volatile MemoryEngineeringEmerging Memory TechnologyTan/tin Bottom ElectrodePhase Change Memory +18

Atomic-level engineering of phase change material for novel fast-switching and high-endurance PCM for storage class memory application

Huai‐Yu Cheng, M. BrightSky, Simone Raoux, +11

Non-volatile MemoryEngineeringEmerging Memory TechnologyPhase Change MemoryStorage Systems +16

A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method—Part I: Fundamental Theory and Applications to Study of the Trapped Charge Vertical Location and Capture Efficiency of SONOS-Type Devices

Hang-Ting Lue, Pei-Ying Du, Szu-Yu Wang, +3

IEEE Transactions on Electron Devices

Detailed Charge-trapping BehaviorEngineeringIntegrated CircuitsTransient Analysis Method—partCharge Transport +17

A novel double-density, single-gate vertical channel (SGVC) 3D NAND Flash that is tolerant to deep vertical etching CD variation and possesses robust read-disturb immunity

Hang-Ting Lue, Tzu‐Hsuan Hsu, Chen-Jun Wu, +18

Non-volatile MemoryElectrical EngineeringSgvc DeviceEngineeringNanoelectronics +13

Modeling of Barrier-Engineered Charge-Trapping nand Flash Devices

Hang-Ting Lue, Sheng-Chih Lai, Tzu‐Hsuan Hsu, +5

IEEE Transactions on Device and Materials Reliability

EngineeringMultilayer BarrierCharge TransportSemiconductor DeviceSemiconductors +14

A novel dual-channel 3D NAND flash featuring both N-channel and P-channel NAND characteristics for bit-alterable Flash memory and a new opportunity in sensing the stored charge in the WL space

Hang-Ting Lue, Pei-Ying Du, Wei-Chen Chen, +6

Novel Dual-channel 3DElectrical EngineeringNon-volatile MemoryEngineeringNegative Vpass +11

A Monte Carlo simulation method to predict large-density NAND product memory window from small-array test element group (TEG) verified on a 3D NAND Flash test chip

Chih-Chang Hsieh, Hang-Ting Lue, Tzu-Hsuan Hsu, +3

Non-volatile MemoryElectrical EngineeringEngineeringMemory Product WindowNanoelectronics +11