Realistic defect coverages of voltage and current tests

Abstract

This paper presents the realistic defect coverage of voltage and current measurements on a Philips digital CMOS ASIC library obtained by defect simulation. This analysis was made to study the minimisation of overlap between voltage and current based test methods by means of defect detection tables. Results show a poor defect coverage of voltage measurements and the major influence of the defect resistance on the voltage detectability and the possible overlap.