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Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs.
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1985
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Low-power ElectronicsDevice ModelingElectrical EngineeringFunctional ModelsEngineeringVlsi DesignGate Oxide ShortsBias Temperature InstabilityComputer EngineeringCmos IcsMicroelectronicsPropagation Delay TimesCircuit SimulationTesting Considerations
This paper examines the electrical characteristics and testing considerations of gate oxide shorts. Gate oxide shorts will cause increased IDD and in the majority of cases will degrade logic voltage levels and propagation delay times, but may not affect functionality. Stuck-at and functional models are therefore inadequate for testing gate oxide shorts in CMOS ICs unless they are used in conjunction with IDD measurements.