Defect classes-an overdue paradigm for CMOS IC testing

TLDR

For more than 30 years, the IC test industry has struggled to establish a reliable approach that guarantees low defect levels, and defect classes differ from traditional fault models. The authors propose a comprehensive CMOS IC testing strategy that uses defect classes derived from measured electrical properties and outlines test pattern requirements for each class. The approach matches testing strategies to defect electrical properties, drawing on Sandia Labs failure analysis, test facility data, and public literature to define test patterns for each defect class.

Abstract

The IC test industry has struggled for move than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the rest strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and test facilities and from public literature. We describe test pattern requirements for each defect class and propose a test paradigm.