STUCK FAULT AND CURRENT TESTING COMPARISON USING CMOS CHIP TEST

Abstract

This paper compares the effectiveness of Stuck Fault and Current Testing, as applied to CMOS ICs. The comparison is performed by testing sequential CMOS chips using patterns developed via both methodis, and evaluating their ability to identify faulty prciduct. The test results are then contrasted to a previous study in which a smaller, combinatorial chip was tested by the same means. The results indicate that, for the investigated set of chips, Current Testing provides a better screen of defective product for some classes of defects, while Stuck Fault Testing is more effective on others.