ESD Simulation using Compact Models: from I/O Cell to Full Chip

Abstract

The modeling of ESD devices, such as MOS transistors, under ESD stress and bias conditions is reviewed. A practical macro-modeling approach composed of industry standard BJT and MOS compact models is presented. SPICE-type circuit level simulations that uses these models is demonstrated. These include examples at both the I/O cell as well as full-chip levels. Predicting ESD circuit performance as well as the inherent circuit simulation challenges are discussed.