CMOS devices below 0.1 μm: how high will performance go?

Abstract

Issues, challenges, and potential directions for further performance gains beyond 0.1 /spl mu/m CMOS are explored. Gate oxide thickness will soon be tunneling-current limited below 20 /spl Aring/, or roughly 7 atomic layers. V/sub dd/ scaling will slow to accommodate pressure on performance from V/sub t/-nonscaling, pushing CMOS to higher electric fields. Highly abrupt, vertically and laterally nonuniform SUPER-HALO doping profiles will be required for control of short-channel effects in the 0.05 /spl mu/m channel-length regime. More than 6-levels of hierarchical wiring, with the top levels limited only by the speed of EM-wave propagation, are needed to deal with interconnect RC delays. Beyond conventional CMOS, several non-mainstream device alternatives such as SOI, SiGe, and low-temperature CMOS are discussed. The potential performance benefit of each in a CMOS circuit is assessed.