CMOS-Compatible Replacement Metal Gate InGaAs-OI FinFET With $I_{ON}=156~\mu \text{A}/\mu \text{m}$ at $V_{DD}= 0.5$ V and $I_{OFF}=100$ nA/$\mu \text{m}$

Vladimir Djara, Veeresh Deshpande, Marilyne Sousa, Daniele Caimi, Lukas Czornomaz, J. Fompeyrine

IEEE Electron Device Letters · 2016 · 41 citations · 18 references

Concepts

Abstract

We report CMOS-compatible n-channel InGaAson-insulator FinFETs obtained using a replacement metal gate fabrication flow. The fabricated devices feature 12-nm-thick SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> spacers, a scaled high-k/metal gate (capacitance equivalent thickness of ~1.5 nm), raised source and drain doped to ~6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> , and fin width scaled down to 15 nm. Very good control of short-channel effects is demonstrated down to a gate length of 50 nm with a minimum subthreshold swing of 92 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V and a drain-induced barrier lowering of 57 mV/V. An ON-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) of 156 μA/μm is also reported for a supply voltage of 0.5 V and a fixed OFF-state current of 100 nA/μm. This I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> value is the highest reported to date for CMOS-compatible InGaAs devices integrated on Si.

References

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