A 500-MHz DDR High-Performance 72-Mb 3-D SRAM Fabricated With Laser-Induced Epitaxial c-Si Growth Technology for a Stand-Alone and Embedded Memory Application

Abstract

For the first time, the smallest 3-D stacked six-transistor (6T) static-random-access-memory (SRAM) cell technology is successfully developed by using a laser crystallization process to grow perfect single-crystal Si layers on the amorphous dielectric Si dioxide layers. The SRAM cell size is 36 F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.36 ¿m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with 100-nm complementary MOS technology. The 3-D SRAM cell consists of three differently layered and 3-D stacked-cell thin-film transistors (TFTs), whose channel area is a perfect single-crystal Si. The electrical characteristics of the pass n-channel MOS TFT and the load p-channel MOS TFT are very close to those of the planar bulk transistors because their channel Si layers are perfect single-crystal films. A 500-MHz high-performance and highly cost effective 72-Mb-density 3-D SRAM, which is comparable to the conventional planar 6T SRAM in electrical performance, was successfully fabricated for a stand-alone and embedded memory, with this 3-D stacked 6T SRAM cell technology, the low-temperature TFT formation process, periphery-only Co salicidation, and the W shunt wordline scheme.