3D Stacked Memory
3D Stacked Memory is a memory subsystem architecture in which multiple layers of memory cells are vertically integrated using through-silicon vias and wafer-level bonding techniques, enabling high-bandwidth, low-latency data access through dense interlayer connectivity.
317
Publications
16.6K
Citations
1.9K
Authors
258
Institutions
Publications per year
2017–2026
111
Variants
Three-dimensional Stacked Memory
Parents
317
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
Uksong Kang, Hoeju Chung, Seongmoo Heo et al. · IEEE Journal of Solid-State Circuits · 2010 · 487 citations
Engineering, Computer Engineering, Electrical Engineering +15
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Guangyu Sun, Xiangyu Dong, Yuan Xie et al. · 2009 · 439 citations
3D-Stacked Memory Architectures for Multi-core Processors
Gabriel H. Loh · 2008 · 436 citations
Duck-Hwan Kim, Jaeha Kung, Sek Chai et al. · ACM SIGARCH Computer Architecture News · 2016 · 355 citations
1–5 of 317
1.9K
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9
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1–5 of 1.9K
258
Samsung (South Korea)
Seoul, South Korea
19 h-index
377 publications
33.3K citations
Georgia Institute of Technology
Atlanta, United States
19 h-index
115 publications
10.9K citations
Carnegie Mellon University
Pittsburgh, United States
18 h-index
76 publications
7.4K citations

Pennsylvania State University
State College, United States
15 h-index
53 publications
5.3K citations
SK Group (South Korea)
Seoul, South Korea
13 h-index
160 publications
5.3K citations
Korea Advanced Institute of Science and Technology
Daejeon, South Korea
12 h-index
44 publications
2.2K citations
Seoul National University
Seoul, South Korea
12 h-index
46 publications
1.5K citations
ETH Zurich
Zurich, Switzerland
11 h-index
19 publications
1.4K citations
1–8 of 258
10 publications · 405 citations
9
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Repository · 7 publications · 187 citations
7
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7 publications · 761 citations
7
h-index
5 publications · 1.2K citations
5
h-index
TACO · 5 publications · 258 citations
5
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