3D Stacked Memory

3D Stacked Memory is a memory subsystem architecture in which multiple layers of memory cells are vertically integrated using through-silicon vias and wafer-level bonding techniques, enabling high-bandwidth, low-latency data access through dense interlayer connectivity.

317

Publications

16.6K

Citations

1.9K

Authors

258

Institutions

Publications per year

2017–2026

111

Variants

Three-dimensional Stacked Memory

Authors

1.9K

  1. YX
    Yuan Xie

    Pennsylvania State University, United States

    20 publications · 1.4K citations

    17

    h-index

  2. OM
    Onur Mutlu

    Carnegie Mellon University, United States

    18 publications · 1.5K citations

    17

    h-index

  3. GS
    Guangyu Sun

    Peking University, China

    9 publications · 1K citations

    9

    h-index

  4. GH
    Gabriel H. Loh

    Advanced Micro Devices (Canada), Canada

    9 publications · 1.4K citations

    9

    h-index

  5. SG
    Saugata Ghose

    Carnegie Mellon University, United States

    9 publications · 728 citations

    9

    h-index

1–5 of 1.9K

Venues

  1. IEEE Transactions on Electron Devices

    10 publications · 405 citations

    9

    h-index

  2. arXiv (Cornell University)

    Repository · 7 publications · 187 citations

    7

    h-index

  3. IEEE Journal of Solid-State Circuits

    7 publications · 761 citations

    7

    h-index

  4. ACM SIGARCH Computer Architecture News

    5 publications · 1.2K citations

    5

    h-index

  5. ACM Transactions on Architecture and Code Optimization

    TACO · 5 publications · 258 citations

    5

    h-index

1–5