8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to <formula formulatype="inline"><tex Notation="TeX">${&gt;}\,$</tex> </formula>1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to <formula formulatype="inline"><tex Notation="TeX">${≪}\,$</tex></formula>100 mV even if all 4 ranks are refreshed every clock cycle consecutively. </para>