2003 · 100 citations · 22 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignConfigurable Logic BlocksLeakage Power ReductionLow-power Digital Circuit DesignLow-power Fpga DesignTiming AnalysisConfigurable Logic Block DesignDesign MethodologyGate-level DesignLeakage Current ReductionLeakage PowerLeakage Power OptimizationMtcmos CircuitsSleep Transistor Design
Multi-threshold CMOS is a popular technique for reducing standby leakage power with low delay overhead. MTCMOS designs typically use large sleep devices to reduce standby leakage at the block level. We provide a formal examination of sneak leakage paths and a design methodology that enables gate-level insertion of sleep devices for sequential and combinational circuits. A fabricated 0.13 /spl mu/m, dual V/sub T/ test chip employs this methodology to implement a low-power FPGA core with gate-level sleep FETs and over 8/spl times/ measured standby current reduction. The methodology allows local sleep regions that reduce leakage in active configurable logic blocks (CLBs) by up to 2.2/spl times/ (measured) for some CLB configurations.
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Design challenges of technology scaling
Shekhar Borkar · IEEE Micro · 1999 · 1.2K citations
Engineering, Computer Engineering, Electrical Engineering +17
Michael D. Powell, Se-Hyun Yang, Babak Falsafi et al. · 2000 · 669 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17
Scaling of stack effect and its application for leakage reduction
S. Narendra, Vivek De, D.A. Antoniadis et al. · 2001 · 332 citations