Sleep Transistor Design
Sleep Transistor Design is a power gating technique in low-power integrated circuit design where a transistor is inserted in series with the power supply of a circuit block to minimize leakage current during standby modes by creating a high-impedance state, thereby distinguishing it from other leakage reduction methods through its explicit use of switch-based power disconnection.
102
Publications
4.7K
Citations
241
Authors
78
Institutions
Publications per year
2017–2026
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Massachusetts Institute of Technology, United States
8 publications · 1.2K citations
8
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7
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7
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1–5 of 241
78
Politecnico di Torino
Turin, Italy
10 h-index
37 publications
796 citations
National Tsing Hua University
Hsinchu, Taiwan
8 h-index
29 publications
650 citations
Massachusetts Institute of Technology
Cambridge, United States
8 h-index
23 publications
3.2K citations

University of Bologna
Bologna, Italy
8 h-index
8 publications
173 citations
Intel (United States)
Santa Clara, United States
5 h-index
44 publications
5.3K citations
Seoul National University
Seoul, South Korea
4 h-index
13 publications
275 citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
4 h-index
13 publications
1K citations
University of Southern California
Los Angeles, United States
4 h-index
8 publications
174 citations
1–8 of 78
8 publications · 286 citations
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6 publications · 1.1K citations
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2 publications · 84 citations
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2 publications · 78 citations
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Repository · 2 publications · 24 citations
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