Concepedia

Leakage Power Optimization

Leakage Power Optimization is a physical design methodology that specifically addresses the minimization of unintended static power consumption in integrated circuits due to subthreshold leakage, gate leakage, and reverse-biased junction leakage, distinguishing it from dynamic power reduction techniques by targeting non-operational current flows.

556

Publications

23.7K

Citations

1.5K

Authors

326

Institutions

Publications per year

2017–2026

59

Variants

Static Power Optimization

Parents

Publications

556

Drowsy caches

Krisztián Flautner, Nam Sung Kim, Steve Martin et al. · ACM SIGARCH Computer Architecture News · 2002 · 742 citations

, , +17

Gated-V<sub>dd</sub>

Michael D. Powell, Se-Hyun Yang, Babak Falsafi et al. · 2000 · 669 citations · Full text

, , +17

Cache decay

Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi · 2001 · 613 citations

, , +17

A new technique for standby leakage reduction in high-performance circuits

Y. Ye, Shekhar Borkar, Vivek De · 2002 · 323 citations

, , +17

Reducing power density through activity migration

Seongmoo Heo, Kenneth C. Barr, Krste Asanović · 2003 · 316 citations

, , +17

1–5 of 556

Authors

1.5K

  1. VD
    Vivek De

    Intel (United States), United States

    19 publications · 1.8K citations

    17

    h-index

  2. SB
    Shekhar Borkar

    Intel (United States), United States

    17 publications · 1.7K citations

    16

    h-index

  3. MI
    M.J. Irwin

    Pennsylvania State University, United States

    19 publications · 892 citations

    14

    h-index

  4. DB
    David Blaauw

    University of Michigan, United States

    15 publications · 1.7K citations

    14

    h-index

  5. DS
    Dennis Sylvester

    University of Michigan, United States

    16 publications · 838 citations

    14

    h-index

1–5 of 1.5K

Institutions

326

  1. Intel (United States)

    Santa Clara, United States

    27 h-index

    139 publications

    9.9K citations

  2. University of Michigan

    Ann Arbor, United States

    22 h-index

    107 publications

    8.2K citations

  3. Pennsylvania State University

    State College, United States

    18 h-index

    108 publications

    4.7K citations

  4. IBM (United States)

    Armonk, United States

    17 h-index

    83 publications

    2.8K citations

  5. Purdue University West Lafayette

    West Lafayette, United States

    16 h-index

    60 publications

    7.4K citations

  6. Politecnico di Torino

    Turin, Italy

    13 h-index

    52 publications

    1.4K citations

  7. Arizona State University

    Tempe, United States

    11 h-index

    27 publications

    841 citations

  8. University of Bologna

    Bologna, Italy

    11 h-index

    19 publications

    374 citations

1–8 of 326

Venues

  1. 21

    h-index

  2. IEEE Journal of Solid-State Circuits

    15 publications · 1.4K citations

    13

    h-index

  3. 13

    h-index

  4. 7

    h-index

  5. IEEE Transactions on Electron Devices

    7 publications · 337 citations

    7

    h-index

1–5