Built-in self testing of high-performance circuits using twisted-ring counters

Abstract

We present an enhanced built-in self-test (BIST) architecture for high-performance circuits. Test patterns are generated by reseeding a twisted-ring counter. We show that a small number of seeds is adequate for generating test sequences that embed complete test sets for the ISCAS benchmark circuits. The seed patterns can either be stored on-chip or scanned in using a low-cost, slower tester. The seeds can thus be viewed as an encoded version of the test set-during testing, the patterns derived from the seeds are applied test-per-clock to the circuit under test. This allows us to effectively combine high-quality BIST with external testing using slower testers.