Self-Testing Circuits is a methodological framework in digital system design that enables a circuit to autonomously generate test patterns, apply them to its own components, and evaluate the responses without reliance on external testing equipment.
204
Publications
9.3K
Citations
444
Authors
165
Institutions
Publications per year
2017–2026
9
Variants
Self-testable Circuits
Parents
Publications
204
McCluskey, Bozorgui-Nesbat · IEEE Transactions on Computers · 1981 · 225 citations
An embedded true random number generator for FPGAs
Paul Kohlbrenner, Kris Gaj · 2004 · 200 citations
Engineering, Computer Engineering, Electrical Engineering +17
1–5 of 204
Authors
444
- KC
8
h-index
- HW
7
h-index
- JP
7
h-index
- CP
6
h-index
- MB
5
h-index
1–5 of 444
Institutions
165
University of Southern California
Los Angeles, United States
10 h-index
20 publications
531 citations
Duke University
Durham, United States
8 h-index
11 publications
506 citations
University of Stuttgart
Stuttgart, Germany
7 h-index
12 publications
533 citations
Case Western Reserve University
Cleveland, United States
6 h-index
14 publications
440 citations
University of Michigan
Ann Arbor, United States
6 h-index
12 publications
328 citations
McGill University
Montreal, Canada
6 h-index
13 publications
883 citations
Stanford University
Stanford, United States
6 h-index
11 publications
876 citations
Politecnico di Torino
Turin, Italy
5 h-index
13 publications
206 citations
1–8 of 165
Venues
- IEEE Transactions on Computers
16 publications · 1.1K citations
14
h-index
- IEEE Design & Test of Computers
11 publications · 746 citations
11
h-index
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
11 publications · 888 citations
11
h-index
- IEEE Transactions on Instrumentation and Measurement
10 publications · 272 citations
10
h-index
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
6 publications · 146 citations
6
h-index
1–5