Logic Bist
Logic Bist is a design-for-testability methodology that integrates self-test capability into digital circuits by embedding on-chip test pattern generation and response analysis circuitry to enable autonomous fault detection and diagnosis.
445
Publications
14.4K
Citations
884
Authors
252
Institutions
Publications per year
2017–2026
31
Parents
445
OPMISR: the foundation for compressed ATPG vectors
C. Barnhart, V. Brunkhorst, F. Distler et al. · 2002 · 344 citations
Engineering, Computer Engineering, Electrical Engineering +14
Logic BIST for large industrial designs: real issues and case studies
G. Hetherington, T. Fryars, N. Tamarapalli et al. · 2003 · 284 citations
Engineering, Computer Engineering, Electrical Engineering +16
A SmartBIST variant with guaranteed encoding
B. Koenemann, C. Barnhart, Brion Keller et al. · 2002 · 269 citations
1–5 of 445
884
17
h-index
14
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12
h-index
12
h-index
11
h-index
1–5 of 884
252
Mentor Technologies
Tulsa, United States
19 h-index
25 publications
1.1K citations
University of Stuttgart
Stuttgart, Germany
18 h-index
22 publications
1.4K citations
IBM (United States)
Armonk, United States
13 h-index
14 publications
965 citations
University of Southern California
Los Angeles, United States
12 h-index
13 publications
722 citations
Synopsys (United States)
Mountain View, United States
12 h-index
14 publications
563 citations
University of Iowa
Iowa City, United States
12 h-index
12 publications
551 citations
Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Montpellier, France
12 h-index
17 publications
475 citations
Duke University
Durham, United States
12 h-index
17 publications
358 citations
1–8 of 252
23 publications · 1K citations
19
h-index
23 publications · 978 citations
17
h-index
JETTA · 19 publications · 445 citations
14
h-index
11 publications · 542 citations
11
h-index
12 publications · 296 citations
11
h-index
1–5