Logic Bist

Logic Bist is a design-for-testability methodology that integrates self-test capability into digital circuits by embedding on-chip test pattern generation and response analysis circuitry to enable autonomous fault detection and diagnosis.

445

Publications

14.4K

Citations

884

Authors

252

Institutions

Publications per year

2017–2026

31

Authors

884

  1. CE
    Charles E. Stroud

    University of Kentucky, United States

    18 publications · 834 citations

    17

    h-index

  2. HW
    Hans-Joachim Wunderlich

    University of Stuttgart, Germany

    14 publications · 957 citations

    14

    h-index

  3. JR
    Janusz Rajski

    Mentor Technologies, United States

    15 publications · 464 citations

    12

    h-index

  4. KC
    Krishnendu Chakrabarty

    Duke University, United States

    17 publications · 358 citations

    12

    h-index

  5. JT
    Jerzy Tyszer

    Poznań University of Technology, Poland

    12 publications · 334 citations

    11

    h-index

1–5 of 884

Venues

  1. IEEE Transactions on Computers

    23 publications · 1K citations

    19

    h-index

  2. 17

    h-index

  3. Journal of Electronic Testing

    JETTA · 19 publications · 445 citations

    14

    h-index

  4. IEEE Design & Test of Computers

    11 publications · 542 citations

    11

    h-index

  5. 11

    h-index

1–5