2003 · 96 citations · 14 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureSystem-on-chip DesignTest ConstructionBuilt-in Self-testCombinational Logic DescriptionDesign For TestabilityDigital Logic DesignLogic SynthesisBinary Counter AnalysisCounter DesignDigital Circuit Self-testingLogic BistLogic Built-in Self-testOn-chip Test Pattern GenerationSelf-test ArchitectureTest Generation
The authors describe a built-in self-test (BIST) technique where the on-chip test pattern generator is a binary counter with associated XOR gates. A precomputed set of tests (obtained through some test generation scheme) is required for this approach. A subset of this set of tests forms the basis for the synthesis of the binary counter and accompanying (combinational) logic using linear algebraic techniques. Simulation of this BIST technique on various benchmark circuits has given good results in terms of both coverage and hardware size.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Built-in test for VLSI: Pseudorandom techniques
Integration · 1989 · 866 citations
Engineering, Computer Engineering, Electrical Engineering +12
Built-in logic block observation techniques
B. Koenemann · Medical Entomology and Zoology · 1979 · 445 citations