Temperature Effects on Breakdown Characteristics of High-$\kappa$ Gate Dielectrics With Metal Gates

Abstract

In this paper, the temperature dependence of time-dependent dielectric breakdown (BD) and stress-induced leakage current (SILC) of high-kappa and interfacial layers (ILs) are studied separately and in a gate stack with metal gates as the BD mechanisms of these layers are different at higher temperatures than at room temperature. As observed from the low voltage SILC, the IL initiates the gate stack BD process at elevated temperature, which is followed by the high-kappa layer. Activation energy extracted from Weibulll distribution of time-to-BD ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> ) data from high-kappa layer further suggests that the gate stack BD occurs when high- kappa layer ultimately breaks down.