IEEE Transactions on Electron Devices · 2011 · 104 citations · 10 references
EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesCarrier TransportDevice ModelingDevice ScalingDevice SimulationMetal-oxide-semiconductor Field-effect TransistorsSemiconductor InterfacesCharge TrappingEquivalent Oxide ThicknessGate Oxide Thickness EffectsHot-carrier DegradationMosfet ModelingThreshold VoltageThreshold Voltage ModelingThreshold Voltage Scaling
Based on the perimeter-weighted-sum method and scaling theory, a compact threshold voltage model for surrounding-gate MOSFETs with localized interface trapped charges is developed by considering the effects of equivalent oxide charges on the flat-band voltage. The model shows how various charge conditions such as the positive/negative trapped charges and device structure parameters such as the silicon thickness, oxide thickness, and channel length affect the threshold voltage behavior. The model is verified by the 3-D device simulator and can be efficiently used to explore hot-carrier-induced threshold voltage degradation of the charge-trapped memory device.
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Scaling theory for double-gate SOI MOSFET's
Ken Suzuki, Tetsu Tanaka, Y. Tosaka et al. · IEEE Transactions on Electron Devices · 1993 · 556 citations · Full text
Engineering, Electrical Engineering, Electronic Materials +16