Threshold Voltage Scaling

Threshold Voltage Scaling is a semiconductor device scaling methodology that specifically governs the proportional reduction of the threshold voltage in field-effect transistors to maintain performance and power efficiency as device dimensions are miniaturized.

352

Publications

21.5K

Citations

1.5K

Authors

298

Institutions

Publications per year

2017–2026

29

Authors

1.5K

  1. AP
    Anantha P. Chandrakasan

    Massachusetts Institute of Technology, United States

    13 publications · 2.4K citations

    12

    h-index

  2. TH
    Toshiro Hiramoto

    The University of Tokyo, Japan

    8 publications · 305 citations

    8

    h-index

  3. DB
    David Blaauw

    University of Michigan, United States

    7 publications · 1.2K citations

    7

    h-index

  4. AS
    Alessandro S. Spinelli

    Politecnico di Milano, Italy

    6 publications · 362 citations

    6

    h-index

  5. KR
    Kaushik Roy

    Purdue University West Lafayette, United States

    6 publications · 423 citations

    6

    h-index

1–5 of 1.5K

Venues

  1. IEEE Transactions on Electron Devices

    48 publications · 5.1K citations

    28

    h-index

  2. Solid-State Electronics

    19 publications · 553 citations

    14

    h-index

  3. IEEE Journal of Solid-State Circuits

    14 publications · 2.7K citations

    13

    h-index

  4. Applied Physics Letters

    13 publications · 608 citations

    12

    h-index

  5. IEEE Electron Device Letters

    14 publications · 958 citations

    12

    h-index

1–5