Threshold Voltage Scaling
Threshold Voltage Scaling is a semiconductor device scaling methodology that specifically governs the proportional reduction of the threshold voltage in field-effect transistors to maintain performance and power efficiency as device dimensions are miniaturized.
352
Publications
21.5K
Citations
1.5K
Authors
298
Institutions
Publications per year
2017–2026
29
352
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Chenming Hu, Jeffrey Bokor, Tsu‐Jae King et al. · IEEE Transactions on Electron Devices · 2000 · 1.6K citations
Engineering, Electrical Engineering, Electronic Materials +13
1–5 of 352
1.5K
Massachusetts Institute of Technology, United States
13 publications · 2.4K citations
12
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8
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7
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6
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6
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1–5 of 1.5K
298
IBM (United States)
Armonk, United States
17 h-index
141 publications
7.9K citations
Intel (United States)
Santa Clara, United States
15 h-index
59 publications
4K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
15 h-index
57 publications
3.1K citations
Massachusetts Institute of Technology
Cambridge, United States
13 h-index
36 publications
4K citations
Hitachi (Japan)
Tokyo, Japan
13 h-index
52 publications
4.6K citations
Georgia Institute of Technology
Atlanta, United States
13 h-index
33 publications
3.2K citations
University of California, Berkeley
Berkeley, United States
10 h-index
33 publications
15.6K citations
Texas Instruments (United States)
Dallas, United States
10 h-index
43 publications
1.7K citations
1–8 of 298
48 publications · 5.1K citations
28
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19 publications · 553 citations
14
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14 publications · 2.7K citations
13
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13 publications · 608 citations
12
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14 publications · 958 citations
12
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1–5