Cryogenic Lifetime Studies of 130 nm and 65 nm nMOS Transistors for High-Energy Physics Experiments

Abstract

The Deep Underground Neutrino Experiment will use unsurpassed quantities of liquid argon to fill a time projection chamber. Research is under way to place the electronics inside the cryostat. For reasons of efficiency and economics, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is hot carrier degradation. It is therefore imperative that studies be performed in candidate technologies to explore hot carrier degradation and to determine if such technologies are suitable for these rigorous requirements. In this paper, 130 nm and 65 nm nMOS transistors operating at cryogenic temperatures are examined. The results show that both technologies achieve the lifetimes required by the experiment. Minimal design changes are necessary in the case of the 130 nm process and no changes whatsoever are necessary for the 65 nm process.