2008 · 10 citations · 6 references
EngineeringIntegrated CircuitsFlip Chip BondingFlip ChipWafer Scale ProcessingAdvanced Packaging (Semiconductors)Electronic PackagingMaterials ScienceElectrical EngineeringCrystalline DefectsChip On BoardLead Free ReflowChip AttachmentAusn SolderSemiconductor Device FabricationMicroelectronicsMicrostructureAdvanced PackagingMicrofabricationApplied PhysicsSi Readout ChipOptoelectronicsSnag Solder
Lead free reflow soldering techniques applying AuSn as well as SnAg electroplated bumps were chosen for the evaluation of the flip chip bonding process for a x-ray pixel detector. Both can be used in pick & place processes with a subsequent batch reflow suitable for high volume production. AuSn solder was selected due to its fluxless bondability, the good wettability and the self-alignment process capability and SnAg solder due to its more ductile behaviour and lower yield stress compared to AuSn. GaAs test chips with daisy chain and four point Kelvin probe structures together with appropriate Si test substrates were designed, manufactured and bumped. Test chips with 55 and 170 μm pitch and different chip sizes (maximum 16.3 down to 4 mm square) were used. AuSn bumps were deposited by electroplating Au first and Sn on top. Au bumps were also formed on substrate side. Two under bump metallizations (UBM) were used for the SnAg samples: Cu and Ni.
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The Influence of Elevated Temperature Aging on Reliability of Lead Free Solder Joints
Hongtao Ma, Jeffrey C. Suhling, Yifei Zhang et al. · 2007 · 151 citations
Studies on a novel flip-chip interconnect structure. Pillar bump
Tengfei Wang, Fletcher Tung, L. Foo et al. · 2002 · 44 citations
Engineering, Mechanical Engineering, Integrated Circuits +16
Precise flip chip assembly using electroplated AuSn20 and SnAg3.5 solder
Matthias Hütter, Hermann Oppermann, G. Engelmann et al. · 2006 · 20 citations