Assembly and reliability of flip chip solder joints using miniaturized Au/Sn bumps

Abstract

Flip chip assembly experiments using small electroplated Au/Sn bumps, i.e. bumps of 50 /spl mu/m in diameter and less, are carried out. After plating the bumps consist of a Au layer with a thinner Sn layer on top. Normally a reflow process in which the bumps are heated up to more than 280/spl deg/C follows after which the bumps consist of a thick Au layer with an eutectic solder cap on top and a /spl zeta/-phase layer in between. However, the experiments prove that due to geometrical reasons as plated bumps rather than reflowed ones shall be used for bump sizes below 50 /spl mu/m in diameter in order to achieve a high yield flip chip assembly process. Furthermore thermal cycling tests were carried out using flip chip assemblies consisting of a GaAs die soldered to a BCB thin film Silicon substrate. Assemblies with Au/Sn bumps of the size of 30 /spl mu/m and 50 /spl mu/m in diameter were tested this way.