Novel dual layer floating gate structure as enabler of fully planar flash memory

Abstract

Flash pitch scaling will lead to cells for which the wordline no longer fits between the floating gates, which results in loss of sidewall coupling, causing unacceptable program saturation due to IPD leakage. We present a dual layer poly/metal floating gate (FG) memory device avoiding this saturation and demonstrate +4V programming above the fresh level in a fully planar cell without sidewall coupling using an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> IPD. The data retention at 200C and cycling performance up to 100k cycles are similar to cells with poly FG.