C. Vrancken

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

T. Chiarella, Liesbeth Witters, A. Mercha et al. · Solid-State Electronics · 2010 · 120 citations

Electrical Engineering, Physical Design (Electronics), Engineering +8

Systematic TLM Measurements of NiSi and PtSi Specific Contact Resistance to n- and p-Type Si in a Broad Doping Range

N. Stavitski, M.J.H. van Dal, A. Lauwers et al. · IEEE Electron Device Letters · 2008 · 97 citations

Engineering, Integrated Circuits, Silicon On Insulator +17

Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

J. A. Kittl, Małgorzata Pawlak, A. Lauwers et al. · IEEE Electron Device Letters · 2005 · 71 citations

Materials Science, Electrical Engineering, Engineering +15

Response of a single trap to AC negative Bias Temperature stress

M. Toledano-Luque, B. Kaczer, Ph. Roussel et al. · 2011 · 71 citations

Electrical Engineering, Engineering, Stress-induced Leakage Current +9

Silicides for the 100-nm node and beyond: Co-silicide, Co(Ni)-silicide and Ni-silicide

A. Lauwers, M. de Potter, O. Chamirian et al. · Microelectronic Engineering · 2002 · 63 citations

Engineering, Physics, Natural Sciences +8