Performance of the 3-D PENCIL flash EPROM cell and memory array

Abstract

A promising new 3-D Programmable Erasable Nonvolatile CylIndricaL (PENCIL) flash EPROM cell that offers significant area and performance advantages over conventional planar approaches has been implemented in a novel memory array. The 3-D PENCIL cell is a vertical device formed on the sidewalls of an etched silicon pillar. The cell is a single transistor stacked gate structure with the floating gate and control gate completely surrounding the pillar. Current flows vertically from the bit line contact at the top of the pillar to the source lying at the bottom of the pillar. When implemented in a novel self-aligned array, the cell size approaches the square of the minimum pitch and has an area less than half that of the conventional NOR type structure. The cell and array architecture also promise to be highly scalable. Experimental data reveals that the cells have up to 3/spl times/ larger read current than comparable planar cells, are suitable for 5 V only operation and have fast program and erase speeds at moderate voltage levels. Uniformity and endurance characteristics are also promising.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>