IEEE Electron Device Letters · 1993 · 17 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignDevice ModelingDevice ScalingMemory DevicesMemory Subsystem DesignPhysical DesignVery-large-scale Integration Layout3D Stacked MemoryFlash Memory DevicesMemory Array ArchitectureMemory Cell DesignMemory Circuit DesignNon-volatile Memory DesignSiliconThree-dimensional Memory
A new 3-D sidewall flash EPROM cell has been implemented in a novel memory array. The sidewall cell is a single-transistor stacked gate cell built on the sidewalls of a silicon pillar. The gates surround the pillar and current flows vertically from top to bottom of the pillar. The cell size approaches the square of the minimum pitch and is less than 40% of that of the conventional NOR-type structure. The cell and array architecture promise to be highly scalable.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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A 90 ns 100 K erase/program cycle megabit flash memory
V. Kynett, J. Anderson, G. Atwood et al. · 2003 · 13 citations
Engineering, Computer Engineering, Electrical Engineering +14
A novel memory cell using flash array contactless EPROM (FACE) technology
B.J. Woo, T.C. Ong, A. Fazio et al. · 2002 · 12 citations
Engineering, Computer Engineering, Electrical Engineering +13