Deterministic and Low Power BIST Based on Scan Slice Overlapping

Abstract

This paper presents a new deterministic pattern generation structure that can be used in conjunction with any LFSR reseeding scheme. The proposed scheme utilizes scan slice overlapping to reduce the number of specified bits and the number of transitions at the same time. Thus, it can significantly reduce test power and evens control signals. Experimental results indicate that the proposed method significantly reduces the switching activity by 80% and only needs relatively small test data storage.