Critical Path Optimization
Critical Path Optimization is a methodological approach in digital circuit design that targets the reduction of delay along the longest combinational path between sequential elements, thereby enabling higher clock frequency and improved timing closure.
431
Publications
15.6K
Citations
1.1K
Authors
347
Institutions
Publications per year
2017–2026
54
Parents
431
Timing-driven placement for FPGAs
Alexander Marquardt, Vaughn Betz, Jonathan Rose · 2000 · 284 citations · Full text
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IBM Research - Thomas J. Watson Research Center, United States
7 publications · 184 citations
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347

University of Minnesota
Minneapolis, United States
15 h-index
42 publications
2.2K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
14 h-index
49 publications
2.7K citations
University of Southern California
Los Angeles, United States
12 h-index
32 publications
2.6K citations
University of Wisconsin–Madison
Madison, United States
11 h-index
19 publications
863 citations

University of Toronto
Toronto, Canada
11 h-index
23 publications
1.8K citations
University of Michigan
Ann Arbor, United States
10 h-index
24 publications
654 citations
Intel (United States)
Santa Clara, United States
10 h-index
20 publications
738 citations
Tsinghua University
Beijing, China
9 h-index
29 publications
569 citations
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29 publications · 954 citations
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20 publications · 992 citations
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12 publications · 330 citations
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9 publications · 254 citations
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ICCAD · 7 publications · 220 citations
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