Critical Path Optimization

Critical Path Optimization is a methodological approach in digital circuit design that targets the reduction of delay along the longest combinational path between sequential elements, thereby enabling higher clock frequency and improved timing closure.

431

Publications

15.6K

Citations

1.1K

Authors

347

Institutions

Publications per year

2017–2026

54

Authors

1.1K

  1. MP
    Massoud Pedram

    University of Southern California, United States

    8 publications · 541 citations

    8

    h-index

  2. VZ
    Vladimir Zolotov

    Motorola (United States), United States

    8 publications · 204 citations

    8

    h-index

  3. CV
    Chandu Visweswariah

    IBM (United States), United States

    8 publications · 287 citations

    8

    h-index

  4. JX
    Jinjun Xiong

    IBM Research - Thomas J. Watson Research Center, United States

    7 publications · 184 citations

    7

    h-index

  5. DZ
    David Z. Pan

    The University of Texas at Austin, United States

    6 publications · 179 citations

    6

    h-index

1–5 of 1.1K